Homework: Exercise L7 (Control Unit)

Theory: How to Approach These

New instruction in RTN (6.2): use only legal transfers; the ALU adds only AC + MBR, and the PC is loaded from the bus.
Microcode in binary (7.1): translate with Table 4.9; an 18-bit word is MicroOp1 (5) | MicroOp2 (5) | Jump (1) | Dest (7); a routine ends with Jump = 1, Dest = 0000000.
Control signals (7.1): source → $P_2P_1P_0$ , destination → $P_5P_4P_3$ , plus $M_R$ / $M_W$ , $T_n$ and $C_r$ on the last step.
Design essays: thesis, arguments, then state and rebut the opposing view.

Jump to: Q1 · Q2 · Q3 · Q4 · Q5

Worked Examples

Exercise Q1

Suppose we add the following instruction to MARIE’s ISA:

JumpOffset X

This instruction will jump to the address calculated by adding the given address, X, to the contents of the accumulator. Show how this instruction would be executed using RTN.

Part	Detail
Asks	Write the register transfers that make PC = X + AC.
Needs	ALU adds only AC + MBR; X is IR[11–0]; the PC loads from the bus.
Look at	X is a value here, not a data address, so no memory read.
If it changes	New instruction: decide what ends where, move operands to MBR/AC, copy the result to its destination.

Show solution ↓

Solution

How to solve

Put X into the MBR so the ALU can use it.
Add: AC ← AC + MBR.
Copy the sum to the PC.

Sample answer

MBR <- X            / X = IR[11-0]
AC  <- AC + MBR     / AC = AC + X
PC  <- AC           / jump to the computed address

These run after the normal fetch and decode. Example: AC = 0005, JumpOffset 100: MBR = 0100, AC = 0105, PC = 105, so the next instruction is fetched from 105.

Watch out: the AC is overwritten with the target address, and only its low 12 bits go into the PC. Do not read memory at X.

Exercise Q2

Using the coding given in Table 4.9, translate into binary the mnemonic microcode instructions given in Figure 4.23 for the fetch-decode cycle (the first nine lines of the table).

Address	MicroOp 1	MicroOp 2	Jump	Dest.
0000000	MAR ← PC	NOP	0	0000000
0000001	IR ← M[MAR]	NOP	0	0000000
0000010	PC ← PC + 1	NOP	0	0000000
0000011	MAR ← IR[11-0]	NOP	0	0000000
0000100	If IR[15-12] = MicroOP2[4-1]	00000	1	0100000
0000101	If IR[15-12] = MicroOP2[4-1]	00010	1	0100111
0000110	If IR[15-12] = MicroOP2[4-1]	00100	1	0101010
0000111	If IR[15-12] = MicroOP2[4-1]	00110	1	0101100
0001000	If IR[15-12] = MicroOP2[4-1]	01000	1	0101111

Address	Jump	Dest.
0000000	0	0000000
0000001	0	0000000
0000010	0	0000000
0000011	0	0000000
0000100	1	0100000
0000101	1	0100111
0000110	1	0101010
0000111	1	0101100
0001000	1	0101111

Part	Detail
Asks	Replace each mnemonic with its 5-bit code; the other columns are already binary.
Needs	NOP 00000, IR ← M[MAR] 00110, MAR ← IR[11–0] 01000, MAR ← PC 01010, PC ← PC + 1 10001, If IR[15–12] = MicroOp2[4–1] 11000.
Look at	Only MicroOp1 (and NOP) need translating; lines 4–8 already hold binary MicroOp2.
If it changes	Other lines: look up codes in Table 4.9; the 5 + 5 + 1 + 7 layout stays.

Show solution ↓

Solution

How to solve

Look up each MicroOp1 code in Table 4.9 (NOP = 00000 in MicroOp2).
Copy Jump and Dest unchanged.
Concatenate into the 18-bit word: 5 + 5 + 1 + 7.

Sample answer

Address	MicroOp 1	MicroOp 2	Jump	Dest.	18-bit word
0000000	01010	00000	0	0000000	010100000000000000
0000001	00110	00000	0	0000000	001100000000000000
0000010	10001	00000	0	0000000	100010000000000000
0000011	01000	00000	0	0000000	010000000000000000
0000100	11000	00000	1	0100000	110000000010100000
0000101	11000	00010	1	0100111	110000001010100111
0000110	11000	00100	1	0101010	110000010010101010
0000111	11000	00110	1	0101100	110000011010101100
0001000	11000	01000	1	0101111	110000100010101111

Lines 4–8 are the jump table: MicroOp2 bits 4–1 hold the opcode tested (0000 JnS → 32, 0001 Load → 39, 0010 Store → 42, 0011 Add → 44, 0100 Subt → 47). Each word is $5+5+1+7 = 18$ bits ✓.

Watch out: keep the field order MicroOp1 | MicroOp2 | Jump | Dest and every leading zero.

Exercise Q3

You and a colleague are designing a brand new microprocessor architecture. Your colleague wants the processor to support 509 different instructions. You do not agree, and would like to have many fewer instructions. Outline the argument for a position paper to present to the management team that will make the final decision. Try to anticipate the argument that could be made to support the opposing viewpoint.

Part	Detail
Asks	An essay outline: your position (fewer instructions), reasons, the other side’s reasons, your replies.
Needs	Hardwired vs microprogrammed control, RISC vs CISC, opcode bits $= \lceil \log_2 n \rceil$ .
Look at	“Anticipate the opposing argument”: include it and rebut it.
If it changes	Defending 509 instead: swap sides, keep the same structure.

Show solution ↓

Solution

How to solve

State a clear thesis.
Give technical arguments with numbers where possible.
List the strongest opposing points with a rebuttal each.
End with a recommendation.

Sample answer

1. Thesis. A small, regular instruction set (tens, not hundreds) is faster, cheaper and quicker to build than one with 509 instructions.

2. Arguments for fewer instructions

Point	Argument
Simpler control	Control can be hardwired, faster than microprogrammed.
Faster clock	Simpler logic has shorter paths, so a higher clock.
Pipelining	Uniform, simple instructions pipeline well (near one per cycle).
Opcode size	509 instructions need $\lceil \log_2 509 \rceil = 9$ bits; 32–64 need 5–6, leaving room for registers and addresses.
Compilers	Use a small subset most of the time; rare instructions still cost chip area.
Area and power	Saved area goes to registers and cache.
Cost	Fewer instructions to design and test: lower cost, fewer bugs, faster to market.

3. Opposing arguments and rebuttals

Opposing argument	Rebuttal
Programs are shorter and use less memory.	Memory is cheap; caches hide the cost.
Fewer instruction fetches.	A pipelined design with caches runs several simple instructions in the time of one complex one.
Complex operations in hardware are faster.	Add only the few that measurements show are really used.
Easier for assembly programmers and compilers.	Compilers generate the code; few people write assembly.
Backward compatibility.	A brand-new architecture has no legacy code.
Microcode makes adding instructions easy.	It slows every instruction.

4. Recommendation. A small, regular instruction set with hardwired, pipelined control; spend the saved area on registers and cache; add specific complex instructions only if benchmarks show a need.

Watch out: an essay with no opposing view and no rebuttal misses the question; “fewer is simpler” alone is not an argument.

Exercise Q4

Using Figure 4.23 as a guide, write the binary microcode for MARIE’s Load instruction. Assume that the microcode begins at instruction line number $0110000_2$ .

Hint: For Load:

MAR ← IR[11-0] or MAR ← X
MBR ← M[MAR]
AC ← MBR

Address	MicroOp 1	MicroOp 2	Jump	Dest.
0110000
0110001
0110010

Part	Detail
Asks	One binary line per microoperation of Load, at 0110000, 0110001, 0110010.
Needs	MAR ← IR[11–0] 01000, MBR ← M[MAR] 01101, AC ← MBR 00010, NOP 00000. Fall through with Jump 0; last line Jump 1, Dest 0000000.
Look at	Only the last line jumps back to fetch.
If it changes	Other instruction: write its RTL, one line per step, last line Jump = 1, Dest = 0000000.

Show solution ↓

Solution

How to solve

Write Load’s three microoperations in order.
Put each code in MicroOp1 with NOP in MicroOp2.
Set Jump = 0 on the first two lines; on the last set Jump = 1, Dest = 0000000 to return to fetch.

Sample answer

Address	MicroOp 1	Jump
0110000	01000 (MAR ← IR[11-0])	0
0110001	01101 (MBR ← M[MAR])	0
0110010	00010 (AC ← MBR)	1

As 18-bit words:

0110000:  01000 00000 0 0000000
0110001:  01101 00000 0 0000000
0110010:  00010 00000 1 0000000

To reach this routine the jump table needs the line 11000 | 00010 | 1 | 0110000 (if opcode = 0001, Load, jump to 0110000).

Watch out: forgetting Jump = 1 on the last line leaves the machine running into the next routine.

Exercise Q5

Which control signals should contain a 1 for each step in executing the JUMPI instruction?

Opcode	Instruction	RTN
1100	JumpI X	MAR ← X MBR ← M[MAR] PC ← MBR

Step	RTN	Time
Fetch	MAR ← PC	$T_0$
	IR ← M[MAR]	$T_1$
Decode IR[15-12]	PC ← PC + 1	$T_2$
Get operand	MAR ← IR[11-0]	$T_3$
Execute	MBR ← M[MAR]	$T_4$
	PC ← MBR	$T_5$

Part	Detail
Asks	For $T_0$ to $T_5$ , mark every control signal that is 1.
Needs	Memory 000, MAR 001, PC 010, MBR 011, AC 100, IR 111. Source → $P_2P_1P_0$ , destination → $P_5P_4P_3$ ; $M_R$ to read memory; $C_r$ on the last step.
Look at	The last step’s destination is the PC (010 → $P_4$ ), not the AC.
If it changes	Another instruction: write its RTL, then fill the same table.

Show solution ↓

Solution

How to solve

Per step, convert the source register to bits on $P_2P_1P_0$ and the destination register to bits on $P_5P_4P_3$ .
Add $M_R$ for a memory read and IncrPC for PC ← PC + 1.
Add $C_r$ on the last step to reset the cycle counter.

Sample answer

Step	RTN	Time	$P_5$	$P_4$	$P_3$	$P_2$	$P_1$	$P_0$	$C_r$	IncrPC	$M_R$
Fetch	MAR ← PC	$T_0$	0	0	1	0	1	0	0	0	0
	IR ← M[MAR]	$T_1$	1	1	1	0	0	0	0	0	1
Decode IR[15-12]	PC ← PC + 1	$T_2$	0	0	0	0	0	0	0	1	0
Get operand	MAR ← IR[11-0]	$T_3$	0	0	1	1	1	1	0	0	0
Execute	MBR ← M[MAR]	$T_4$	0	1	1	0	0	0	0	0	1
	PC ← MBR	$T_5$	0	1	0	0	1	1	1	0	0

How each row is found:

$T_0$ : read PC (010 → $P_1$ ), write MAR (001 → $P_3$ ).
$T_1$ : read memory (000, so $M_R$ ), write IR (111 → $P_5P_4P_3$ ).
$T_2$ : no bus transfer; IncrPC adds 1 to the PC while IR[15-12] is decoded.
$T_3$ : read IR (111 → $P_2P_1P_0$ ), write MAR (001 → $P_3$ ).
$T_4$ : read memory (000, so $M_R$ ), write MBR (011 → $P_4P_3$ ).
$T_5$ : read MBR (011 → $P_1P_0$ ), write PC (010 → $P_4$ ), and $C_r$ ends the instruction.

$M_W$ and $L_{ALT}$ stay 0 throughout: JumpI does not write memory or use the ALU.

Watch out: list only signals that are 1 (MBR = 011 is $P_4P_3$ , not $P_5$ ); $C_r$ only on the last step.