Homework: Exercise L6b

Theory: How to Approach These

Register widths (6.2): address registers (MAR, PC) are sized by the number of memory locations; data registers (AC, MBR, IR) by the word size.
Fetch–decode–execute (6.3): name the register that changes in each microoperation and the value it receives; a numeric trace is the clearest proof.
Timing diagrams (7.1): list each cycle’s signals, then draw one waveform per signal, high exactly where it is listed.

Jump to: Q1 · Q2 · Q3

Worked Examples

Exercise Q1

Explain why, in MARIE, the MAR is only 12 bits wide while the AC is 16 bits wide.

Part	Detail
Asks	Explain the two widths from what each register holds.
Needs	MARIE: 4K words of memory, 16-bit words, instruction = 4-bit opcode + 12-bit address.
Look at	MAR holds an address; AC holds data.
If it changes	Bigger memory widens MAR and PC (16K words → 14 bits); bigger words widen AC, MBR, IR.

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Solution

How to solve

Say what the MAR holds (an address) and count the memory locations: $4096 = 2^{12}$ .
Say what the AC holds (a data word) and give the word size, 16 bits.
Summarise as a rule.

Sample answer

The MAR holds a memory address. MARIE has 4K $= 4096 = 2^{12}$ words, so 12 bits name every location ( $\text{000}_{16}$ to $\text{FFF}_{16}$ ). This matches the 12-bit address field of an instruction.

The AC holds a data word. MARIE’s words and ALU are 16 bits (two’s complement, $-32768$ to $+32767$ ), so the AC must be 16 bits.

MAR width = $\log_2(\text{memory words}) = 12$ ; AC width = word size = 16. The PC is also 12 bits; the MBR and IR are 16 bits.

Watch out: do not say the registers differ “because of the opcode”; the reason is address versus data.

Exercise Q2

Explain the steps of the fetch-decode-execute cycle. Your explanation should include what is happening in the various registers.

Part	Detail
Asks	Describe each stage and which register changes to what.
Needs	RTN of fetch, decode, get operand, execute (6.3).
Look at	“Include what is happening in the registers”: use a trace table with real numbers.
If it changes	Only the execute step differs per instruction; fetch and decode are the same.

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Solution

How to solve

Fetch: put the PC in the MAR, read the instruction into the IR, increment the PC.
Decode: copy the address field to the MAR and decode the opcode.
Get operand: read memory into the MBR if the instruction needs data.
Execute: do the instruction’s own transfers, then return to fetch (unless Halt).
Show a worked trace with numbers.

Sample answer

Fetch: MAR ← PC; IR ← M[MAR]; PC ← PC + 1.
Decode: MAR ← IR[11–0]; the control unit decodes the opcode IR[15–12].
Get operand: MBR ← M[MAR] (Load, Add, Subt, …).
Execute: e.g. AC ← MBR (Load), AC ← AC + MBR (Add). Then back to fetch.

Example: Load 104 at address 100, M[104] = 0023.

Step	RTN	PC	IR	MAR	MBR	AC
start		100	----	----	----	----
Fetch	MAR ← PC	100	----	100	----	----
	IR ← M[MAR]	100	1104	100	----	----
	PC ← PC + 1	101	1104	100	----	----
Decode	MAR ← IR[11–0]	101	1104	104	----	----
Operand	MBR ← M[MAR]	101	1104	104	0023	----
Execute	AC ← MBR	101	1104	104	0023	0023

Roles: PC next instruction; MAR address being accessed; IR current instruction; MBR data to or from memory; AC working value and result.

Watch out: the PC is incremented during fetch, so it already points past the current instruction when it executes.

Exercise Q3

Draw the timing diagram for MARIE’s Load instruction using the format of Figure 4.16.

Part	Detail
Asks	Draw each control signal high/low over the clock cycles of Load’s execution.
Needs	Load: MAR ← X; MBR ← M[MAR]; AC ← MBR. Source → $P_2P_1P_0$ , destination → $P_5P_4P_3$ , $M_R$ to read memory, $C_r$ on the last step.
Look at	Figure 4.16 is Add; Load’s last step uses the bus only (no ALU, no $A_0$ , no $L_{ALT}$ ).
If it changes	Any instruction: write its RTL, list signals per $T$ , draw one row per signal.

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Solution

How to solve

Write the RTL; fetch and decode use $T_0$ – $T_2$ , so execution starts at $T_3$ .
For each step, source number → $P_2P_1P_0$ and destination number → $P_5P_4P_3$ (memory 0, MAR 1, PC 2, MBR 3, AC 4, IR 7).
Add $M_R$ for a memory read and $C_r$ on the last step.
Draw each signal high in exactly the cycles that list it.

Cycle	RTL	Source → $P_2P_1P_0$	Dest → $P_5P_4P_3$	Extra	Signals = 1
$T_3$
$T_4$
$T_5$

Sample answer

Cycle	RTL	Read	Write	Extra	Signals
$T_3$	MAR ← X	IR = 111 → $P_2P_1P_0$	MAR = 001 → $P_3$		$P_3\ P_2\ P_1\ P_0\ T_3$
$T_4$	MBR ← M[MAR]	memory = 000	MBR = 011 → $P_4P_3$	$M_R$	$P_4\ P_3\ T_4\ M_R$
$T_5$	AC ← MBR	MBR = 011 → $P_1P_0$	AC = 100 → $P_5$	$C_r$	$P_5\ P_1\ P_0\ T_5\ C_r$

$A_0$ , $A_1$ , $M_W$ and $L_{ALT}$ stay low throughout.

Watch out: the MBR → AC move is over the bus ( $P_1P_0$ ), not through the ALU, so there is no $A_0$ or $L_{ALT}$ .