4.5 Sequential Circuits: Clocks & Flip-Flops

Theory: Sequential Circuits: Clocks & Flip-Flops

Combinational circuits are perfect when we want the immediate result of a Boolean function applied to the current inputs. But a computer also has to remember: register contents, the program counter, which step of an instruction it is executing. A sequential circuit produces outputs that depend on its current inputs and its current state, the stored result of what happened before. Memory is created by feedback: feeding a gate’s output back into the circuit’s own inputs (Null & Lobur, Ch. 3).

	Combinational	Sequential
Output depends on	current inputs only	current inputs and current state
Memory	none	yes (flip-flops)
Feedback paths	none	yes
Timing	output follows inputs after a gate delay	state changes only on clock ticks
Examples	adder, decoder, mux, ALU	flip-flop, register, counter

The Clock

Sequential circuits need a way to sequence events: to decide when the state is allowed to change. This is the job of a clock, a special circuit that sends a regular train of electrical pulses through the system.

        ┌───┐   ┌───┐   ┌───┐   ┌───┐
clock   │   │   │   │   │   │   │   │
     ───┘   └───┘   └───┘   └───┘   └───
        ↑   ↓
     rising falling
      edge   edge
        |<----->|
        one clock cycle (period)

• The period (cycle time) is the time for one complete pulse; the frequency is cycles per second ($1/\text{period}$). An 800 MHz clock has a period of $1/(800 \times 10^6) = 1.25$ ns.
• State changes occur only when the clock ticks.

When exactly does a circuit react?

Type	Changes state…
Edge-triggered	at the instant of the rising edge (low → high) or the falling edge (high → low)
Level-triggered	whenever the clock is at its high level (the whole time the pulse is high)

Edge-triggered devices sample their inputs at one precise instant per cycle, so inputs may change freely at other times without affecting the state. Flip-flops in a CPU are usually edge-triggered.

Mini-example

A rising-edge-triggered device with a 2 ns period changes state at $t = 0, 2, 4, 6, \ldots$ ns, once per cycle, no matter how many times its inputs wiggle between edges.

The SR Flip-Flop: Memory from Feedback

The most basic memory element is the SR (Set/Reset) flip-flop. Its internals are two NOR gates cross-coupled so each one’s output feeds back into the other:

• NOR gate 1 has inputs $S$ and $Q$; its output is $Q'$: $\quad Q' = (S + Q)'$
• NOR gate 2 has inputs $R$ and $Q'$; its output is $Q$: $\quad Q = (R + Q')'$

Recall a NOR outputs 1 only when all its inputs are 0. So any input at 1 forces that gate’s output to 0.

• $S = 1, R = 0$ (set): NOR 1 sees $S = 1$ → $Q' = 0$. NOR 2 sees $R = 0, Q' = 0$ → $Q = 1$. The flip-flop is set to 1.
• $S = 0, R = 1$ (reset): NOR 2 sees $R = 1$ → $Q = 0$. NOR 1 sees $S = 0, Q = 0$ → $Q' = 1$. Reset to 0.
• $S = 0, R = 0$ (hold): each gate just inverts the other’s output, so whatever value is stored keeps reinforcing itself. This is memory.
• $S = 1, R = 1$: both gates are forced to 0, so $Q = Q' = 0$ (not complements!). When the inputs then return to 0 the result depends on which gate is faster: the state is unpredictable, so this input is not allowed.

Characteristic table ($Q(t)$ = output now, $Q(t+1)$ = output after the next clock pulse):

$S$	$R$	$Q(t+1)$
0	0	$Q(t)$ (no change)
0	1	0 (reset)
1	0	1 (set)
1	1	undefined

Because the next state depends on the present state too, the SR flip-flop really has three inputs: $S$, $R$ and $Q(t)$. Its full truth table:

$S$	$R$	$Q(t)$	$Q(t+1)$
0	0	0	0
0	0	1	1
0	1	0	0
0	1	1	0
1	0	0	1
1	0	1	1
1	1	0	undefined
1	1	1	undefined

The block symbol of every flip-flop is a rectangle with its inputs on the left, a small triangle ”>” marking the clock input C, and two outputs $Q$ and $Q'$ (drawn $\overline{Q}$, often with a bubble) on the right.

The JK Flip-Flop

We cannot always guarantee that $S$ and $R$ will never both be 1. The JK flip-flop (named in honour of Jack Kilby, inventor of the integrated circuit) modifies the SR flip-flop so that every input combination is stable.

Construction: two AND gates in front of an SR flip-flop, with feedback from the outputs:

$$S = J \cdot Q', \qquad R = K \cdot Q$$

Since $Q$ and $Q'$ are never both 1, $S$ and $R$ can never both be 1. With $J = K = 1$: if $Q = 0$ then $S = 1, R = 0$ → set to 1; if $Q = 1$ then $S = 0, R = 1$ → reset to 0. Either way the output toggles.

$J$	$K$	$Q(t+1)$
0	0	$Q(t)$ (no change)
0	1	0 (reset)
1	0	1 (set)
1	1	$Q(t)'$ (complement / toggle)

The D Flip-Flop

The D (data) flip-flop is another modification of the SR flip-flop: a single input $D$ drives $S$ directly and $R$ through an inverter:

$$S = D, \qquad R = D'$$

So $S$ and $R$ are always opposite (never both 1), and the flip-flop simply stores whatever is on $D$ at the clock pulse:

$D$	$Q(t+1)$
0	0
1	1

The output stays the same over later clock pulses until $D$ changes. The D flip-flop is the fundamental circuit of computer memory: each one stores one bit.

The T Flip-Flop (JK with J = K)

Tie $J$ and $K$ together into one input $T$ (toggle). Only the rows $JK = 00$ and $JK = 11$ remain:

$T$	$Q(t+1)$
0	$Q(t)$ (hold)
1	$Q(t)'$ (toggle)

This “toggle when told to” behaviour is exactly what a binary counter needs.

Characteristic Equations

Each characteristic table can be written as a single equation for the next state $Q^+ = Q(t+1)$ (derived in Worked Example 7):

Flip-flop	Characteristic equation
SR	$Q^+ = S + R'Q$ (with $SR = 0$)
JK	$Q^+ = JQ' + K'Q$
D	$Q^+ = D$
T	$Q^+ = T \oplus Q$

Mini-example

JK with $J = 1, K = 1, Q = 1$: $Q^+ = 1\cdot 0 + 0 \cdot 1 = 0$ (toggled) ✓. JK with $J = 0, K = 0, Q = 1$: $Q^+ = 0 + 1\cdot 1 = 1$ (held) ✓.

Registers

A register is a group of flip-flops that store a multi-bit word together. A 4-bit register is four D flip-flops with a shared clock: inputs $In_0..In_3$ go to the four $D$ inputs, and the outputs $Out_0..Out_3$ are the four $Q$s. On each clock pulse all four bits are loaded at once; between pulses the stored word is held regardless of what the inputs do. Larger memories are arrays of such registers selected by address decoders.

Binary Counter

A binary counter is a sequential circuit that adds 1 to its stored number on every clock pulse: $0000, 0001, 0010, 0011, \ldots, 1111, 0000, \ldots$

The lecture’s 4-bit counter uses four JK flip-flops ($B_0$ = low-order bit) all on the same clock, each used as a T flip-flop ($J = K$):

Flip-flop	$J = K =$	Toggles when…
$B_0$	Count Enable	every clock pulse (while counting is enabled)
$B_1$	Count Enable $\cdot B_0$	$B_0 = 1$
$B_2$	Count Enable $\cdot B_0 B_1$	$B_0 = B_1 = 1$
$B_3$	Count Enable $\cdot B_0 B_1 B_2$	$B_0 = B_1 = B_2 = 1$

Output Carry $=$ Count Enable $\cdot B_0B_1B_2B_3$: it is 1 when the counter is at $1111$ and about to wrap to $0000$ (for chaining counters).

So the low-order bit is complemented at each clock pulse, and each higher bit is complemented exactly when all the bits below it are 1. This is ordinary binary “add 1”: adding 1 flips the trailing 1s to 0 and the first 0 to 1. Equivalently, each bit flips at the moment the bit below it changes from 1 to 0 (a carry out of the lower bit).

Mini-example

At $0011$: $B_0 = 1$ toggles; $B_1$ toggles (since $B_0 = 1$); $B_2$ toggles (since $B_0 B_1 = 1$); $B_3$ does not ($B_2 = 0$). New value $B_3B_2B_1B_0 = 0100$, i.e. $3 \to 4$ ✓.

Analysing a Clocked Sequential Circuit

Given a circuit diagram of flip-flops and gates, we describe its behaviour with a next-state table (state table).

Procedure:

1. Identify the state variables (one per flip-flop output, e.g. $A$, $B$) and the external inputs (e.g. $X$).
2. Read the wiring and write the input equations: an expression for every flip-flop input ($J_A$, $K_A$, $D_B$, …) in terms of the present state and the inputs.
3. Make a table with one row for every combination of present state and input ($2^{\text{flip-flops} + \text{inputs}}$ rows).
4. For each row, evaluate the input equations.
5. Apply each flip-flop’s characteristic table to get its next state.

All flip-flops share the same clock and change simultaneously. Every input equation must be evaluated with the present values of the state variables, never with a value another flip-flop is about to change to.

Mini-example

One D flip-flop with $D = A \oplus X$. Row $A = 1, X = 1$: $D = 0$, so $A^+ = 0$. Row $A = 1, X = 0$: $D = 1$, $A^+ = 1$. When $X = 1$ the flip-flop toggles; when $X = 0$ it holds: a T flip-flop built from a D flip-flop.

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Worked Examples

Exercise 1

An SR flip-flop built from two cross-coupled NOR gates ($Q' = (S + Q)'$, $Q = (R + Q')'$) starts with $Q = 0$. Trace both gate outputs for the input sequence $SR = 10$, then $00$, then $01$, then $00$.

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Solution

Evaluate the gate whose input is forced first (a NOR with any input 1 outputs 0), then the other.

Step	$S$	$R$	First gate settles	Second gate settles	$Q$	$Q'$	Meaning
start					0	1	stored 0
1	1	0	NOR 1: $(1 + 0)' = 0 = Q'$	NOR 2: $(0 + 0)' = 1 = Q$	1	0	set
2	0	0	NOR 1: $(0 + 1)' = 0 = Q'$	NOR 2: $(0 + 0)' = 1 = Q$	1	0	hold (remembers the 1)
3	0	1	NOR 2: $(1 + 0)' = 0 = Q$	NOR 1: $(0 + 0)' = 1 = Q'$	0	1	reset
4	0	0	NOR 2: $(0 + 1)' = 0 = Q$	NOR 1: $(0 + 0)' = 1 = Q'$	0	1	hold (remembers the 0)

Steps 2 and 4 have the same inputs ($SR = 00$) but different outputs: the output depends on the history. That is memory, and it is why a flip-flop is a sequential, not combinational, circuit.

If we had applied $SR = 11$: both NOR gates would be forced to 0, giving $Q = Q' = 0$; on returning to $00$ the final state would depend on gate timing, which is why $SR = 11$ is undefined.

Exercise 2

A JK flip-flop starts with $Q = 0$. The following $(J, K)$ values are present at six successive clock pulses: $(1,0), (0,0), (1,1), (1,1), (0,1), (1,1)$. Give $Q$ after each pulse.

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Solution

Apply the JK table with $Q(t)$ = the value before the pulse.

Pulse	$J$	$K$	$Q(t)$	Rule	$Q(t+1)$
1	1	0	0	set	1
2	0	0	1	no change	1
3	1	1	1	toggle	0
4	1	1	0	toggle	1
5	0	1	1	reset	0
6	1	1	0	toggle	1

Output sequence: $1, 1, 0, 1, 0, 1$.

Cross-check with internals at pulse 3 ($J = K = 1$, $Q = 1$): $S = JQ' = 1 \cdot 0 = 0$, $R = KQ = 1 \cdot 1 = 1$ → SR reset → $Q = 0$ ✓.

Exercise 3

A 4-bit register of rising-edge-triggered D flip-flops holds $0000$. The inputs $In_3In_2In_1In_0$ change as follows: $1011$ just before clock edge 1; $0110$ halfway between edges 1 and 2; $1110$ shortly after that, still before edge 2; unchanged before edge 3. Give the register output after each edge and in between.

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Solution

Each D flip-flop copies its $D$ input only at a rising edge ($Q^+ = D$). Between edges, input changes are ignored.

Time	Inputs	Register output $Out_3..Out_0$
initially	(anything)	0000
edge 1	1011	1011 (all four bits loaded at once)
between edges 1 and 2	0110, then 1110	still 1011 (no edge, so no change)
edge 2	1110	1110
edge 3	1110	1110 (same input, same stored value)

The intermediate value $0110$ is never stored, because it was not present at an edge. This is what “edge-triggered” buys us: the inputs only have to be stable around the edge. (A level-triggered register would instead follow the inputs for the whole time the clock is high.)

Exercise 4

The lecture’s 4-bit JK binary counter (Count Enable $= 1$) holds $B_3B_2B_1B_0 = 0110$. For the next four clock pulses, give each flip-flop’s $J = K$ input and the new count. Also give the value of Output Carry when the counter holds $1111$.

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Solution

$J_0 = K_0 = 1$; $J_1 = K_1 = B_0$; $J_2 = K_2 = B_0B_1$; $J_3 = K_3 = B_0B_1B_2$ (all with Count Enable $= 1$). A flip-flop with $J = K = 1$ toggles, with $J = K = 0$ holds. All inputs use the present count.

Pulse	Present $B_3B_2B_1B_0$	$T_3 = B_0B_1B_2$	$T_2 = B_0B_1$	$T_1 = B_0$	$T_0$	Next $B_3B_2B_1B_0$	decimal
1	0110	0	0	0	1	0111	6 → 7
2	0111	1	1	1	1	1000	7 → 8
3	1000	0	0	0	1	1001	8 → 9
4	1001	0	0	1	1	1010	9 → 10

Pulse 2 is the interesting one: all three lower bits are 1, so all four flip-flops toggle at once: $0111 \to 1000$, exactly like the carry in $7 + 1 = 8$.

At $1111$: Output Carry $=$ Count Enable $\cdot B_0B_1B_2B_3 = 1$, and the next pulse toggles all four bits to $0000$ (15 → 0, wrap-around), with the carry signalling the overflow to a following counter stage.

Exercise 5

Analyse the circuit with two D flip-flops $A$ and $B$, input $X$, and input equations

$$D_A = A \oplus (X \cdot B), \qquad D_B = B \oplus X.$$

Build the next-state table and describe what the circuit does.

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Solution

Step 1: state variables $A, B$; input $X$. Step 2: input equations given. Steps 3-5: 8 rows; for D flip-flops $A^+ = D_A$, $B^+ = D_B$.

$A$	$B$	$X$	$XB$	$D_A = A \oplus XB$	$D_B = B \oplus X$	$A^+$	$B^+$
0	0	0	0	0	0	0	0
0	0	1	0	0	1	0	1
0	1	0	0	0	1	0	1
0	1	1	1	1	0	1	0
1	0	0	0	1	0	1	0
1	0	1	0	1	1	1	1
1	1	0	0	1	1	1	1
1	1	1	1	0	0	0	0

Interpretation: read $AB$ as a 2-bit number.

• $X = 0$: $AB^+ = AB$ (00→00, 01→01, 10→10, 11→11): the state holds.
• $X = 1$: 00→01→10→11→00: the state counts up by 1 and wraps.

This is a 2-bit binary counter with count enable $X$, the same structure as the lecture’s counter ($B$ toggles when enabled; $A$ toggles when enabled and $B = 1$).

Exercise 6

Analyse the circuit with two JK flip-flops $A$ and $B$, input $X$, and input equations

$$J_A = X B, \quad K_A = X, \qquad J_B = X, \quad K_B = A.$$

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Solution

Evaluate the four flip-flop inputs from the present $A, B, X$, then apply the JK rule (00 hold, 01 reset, 10 set, 11 toggle) to each flip-flop separately.

$A$	$B$	$X$	$J_A = XB$	$K_A = X$	$A^+$	$J_B = X$	$K_B = A$	$B^+$
0	0	0	0	0	0 (hold)	0	0	0 (hold)
0	0	1	0	1	0 (reset)	1	0	1 (set)
0	1	0	0	0	0 (hold)	0	0	1 (hold)
0	1	1	1	1	1 (toggle 0→1)	1	0	1 (set)
1	0	0	0	0	1 (hold)	0	1	0 (reset)
1	0	1	0	1	0 (reset)	1	1	1 (toggle 0→1)
1	1	0	0	0	1 (hold)	0	1	0 (reset)
1	1	1	1	1	0 (toggle 1→0)	1	1	0 (toggle 1→0)

Next-state summary ($AB \to A^+B^+$):

Present $AB$	$X = 0$	$X = 1$
00	00	01
01	01	11
10	10	01
11	10	00

Check one row with characteristic equations, row $A B X = 101$: $A^+ = J_AA' + K_A'A = 0\cdot0 + 0\cdot1 = 0$ ✓; $B^+ = J_BB' + K_B'B = 1\cdot1 + 0\cdot0 = 1$ ✓.

Exercise 7

Derive the characteristic equations of the SR and JK flip-flops from their full truth tables using K-maps, and show that a JK flip-flop with $J = K = T$ satisfies $Q^+ = T \oplus Q$.

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Solution

SR ($Q^+$ as a function of $S, R, Q$; the two “undefined” rows can never occur, so they are don’t-cares d):

$S \backslash RQ$	00	01	11	10
0	0	1	0	0
1	1	1	d	d

• Group A: whole bottom row (using both d’s) → $S$.
• Group B: column 01 (both rows) → $R = 0, Q = 1$ → $R'Q$.

$$Q^+ = S + R'Q$$

JK (1s at $JKQ$ = 001 hold-1, 100 set, 101 set, 110 toggle 0→1):

$J \backslash KQ$	00	01	11	10
0	0	1	0	0
1	1	1	0	1

• Group A: cells $J KQ = 100$ and $110$ (bottom row, columns 00 and 10, joined by wrap-around) → $J = 1, Q = 0$ → $JQ'$.
• Group B: column 01 (both rows) → $K = 0, Q = 1$ → $K'Q$.

$$Q^+ = JQ' + K'Q$$

Every 1 is covered (cell 101 is in group B) ✓. Read it as: “become 1 if told to set while 0, or stay 1 if not told to reset”.

T flip-flop: substitute $J = K = T$:

$$Q^+ = TQ' + T'Q = T \oplus Q$$

(definition of XOR). Check: $T = 0$ gives $Q^+ = Q$ (hold), $T = 1$ gives $Q^+ = Q'$ (toggle) ✓.