6.1 CPU Basics, Buses, Clocks, I/O & Memory

Theory: CPU Basics, Buses, Clocks, I/O & Memory

Before we can study MARIE (our model computer), we need the vocabulary that every computer shares. Every computer, from a microcontroller to a server, has the same four ingredients (Null & Lobur, Ch. 4):

Component	Job
CPU (control unit + ALU + registers)	fetches, decodes and executes program instructions
Main memory	stores the program and its data (stored-program concept)
I/O subsystem	gets data and instructions into the system and results out
Buses	the wires that connect all of the above

The CPU: Datapath and Control Unit

The CPU’s job is to fetch an instruction from memory, decode it (work out what it means) and execute it, over and over. To do this it is split into two principal parts:

1. The datapath: the “muscle”. It is a network of
   • an arithmetic-logic unit (ALU) that performs arithmetic (add, subtract, …) and logic (AND, OR, NOT, …) operations,
   • registers: small, very fast storage cells inside the CPU,
   • the bus wiring that connects the ALU, the registers and main memory.
2. The control unit (CU): the “brain”. It does not compute anything itself; it decides which actions the datapath carries out and when, based on the instruction being executed, the program counter (address of the next instruction) and a status register (flags such as “result was negative” or “overflow occurred”).

Think of the datapath as a kitchen (ingredients = registers, stove = ALU, corridors = buses) and the control unit as the chef reading the recipe (the program) and telling each station what to do at each tick of the clock.

Registers are built from D flip-flops

A register is just a row of D flip-flops sharing one clock (Lectures 4–5): on each clock edge every flip-flop copies its D input, so the whole word is loaded at once. An $n$-bit register needs $n$ D flip-flops.

Mini-example

A 32-bit register needs 32 D flip-flops. A 16-bit register needs 16. If a CPU has eight 32-bit general-purpose registers, the register file alone contains $8 \times 32 = 256$ flip-flops.

Buses

A bus is a set of wires that carries bits between components, one bit per wire, all wires at the same time (in parallel). A bus that is $n$ wires wide moves an $n$-bit value in one transfer.

Kinds of lines in a bus. A system bus is really three groups of lines:

Lines	What they carry	Direction
Data lines	the actual bits being moved (an instruction, a number)	both ways
Address lines	where the data comes from or goes to (a memory location or device)	usually CPU → memory/devices
Control lines	what to do and when: read vs write, which device may use the bus, clock, interrupt requests	mixed

Two bus topologies:

	Point-to-point bus	Multipoint (shared) bus
Connects	exactly two components	many components on the same wires
Access control	none needed, the link is private	needed: only one device may drive the bus at a time, so protocols built into the hardware (bus arbitration) decide who talks
Cost	many separate links, lots of wiring	cheap: one set of wires shared by all
Speed	no waiting, links run in parallel	devices may have to wait for the bus (it can become a bottleneck)
Example	CPU ↔ dedicated graphics link	MARIE’s single common data bus

Mini-example

A computer has 10 devices. Fully connecting them point-to-point needs one link per pair: $\binom{10}{2} = \dfrac{10 \cdot 9}{2} = 45$ links. A single multipoint bus needs one set of wires, but only one device can transmit at a time.

Clocks

Every computer has at least one clock that produces a regular square wave. Every data movement or computation takes a fixed number of clock cycles, so the clock sets the pace of the whole machine.

• Clock frequency $f$ is measured in hertz (cycles per second): MHz $= 10^6$ Hz, GHz $= 10^9$ Hz.
• Clock cycle time (period) $t$ is the reciprocal of the frequency:

$$t = \frac{1}{f}$$

Mini-example (as in the lecture)

An 800 MHz clock has a cycle time of

$$t = \frac{1}{800 \times 10^6\ \text{Hz}} = 1.25 \times 10^{-9}\ \text{s} = 1.25\ \text{ns}.$$

Useful shortcut: $t\,[\text{ns}] = \dfrac{1000}{f\,[\text{MHz}]}$. So 1000 MHz (1 GHz) → 1 ns, 500 MHz → 2 ns, 2 GHz → 0.5 ns.

A faster clock does not automatically mean a faster program. Execution time = (number of instructions) × (cycles per instruction) × (cycle time). A machine with a slower clock can still win if it needs fewer cycles per instruction.

The Input/Output Subsystem

A computer talks to the outside world (keyboard, display, disk, network) through its I/O subsystem. Devices do not connect to the CPU directly; they connect through interfaces that convert between the device’s signals and the computer’s bus. Typical interfaces from the lecture:

Interface	Kind	Typical speed
RS-232	serial port	up to about 115.2 kbit/s
USB (USB-C)	serial bus	up to about 10 Gbit/s
RJ-45	wired Ethernet connector	100 Mbit/s – 10 Gbit/s
Wi-Fi	wireless network	hundreds of Mbit/s and up

In MARIE the I/O subsystem is reduced to two 8-bit registers: InREG (data arriving from an input device) and OutREG (data waiting for an output device).

Mini-example

How long does RS-232 at 115.2 kbit/s need for 1 KB (1024 bytes = 8192 bits) of raw data? $\ 8192 / 115\,200 \approx 0.071$ s. (Real serial links add a start and stop bit to each byte, i.e. 10 bits per byte: $10240 / 115\,200 \approx 0.089$ s.)

Memory Organization

Main memory is a linear array of addressable storage cells, each one similar to a register. Each cell has an address (its index) and a content (the bits stored there).

Addressability. The unit that one address refers to:

• Byte-addressable: every byte has its own address (most modern machines).
• Word-addressable: every word (typically 2 or more bytes) has its own address. MARIE is word-addressable with 16-bit words.

Length × width. Memory (and the RAM chips it is built from) is described as length × width = (number of addressable locations) × (bits per location). A 4M × 16 memory has $4\text{M} = 4 \times 2^{20}$ locations, each 16 bits wide.

How many address lines? To give every one of $N$ locations a unique binary address you need

$$\text{address bits} = \log_2 N \quad (\text{rounded up if } N \text{ is not a power of } 2).$$

Mini-example (as in the lecture)

A 4M × 16 word-addressable memory: $4\text{M} = 2^2 \times 2^{20} = 2^{22}$ words, so the memory bus needs at least 22 address lines, and the addresses run from $0$ to $2^{22} - 1$.

The same memory made byte-addressable: each 16-bit word is 2 bytes, so there are $2^{22} \times 2 = 2^{23}$ bytes → 23 address lines.

The width of memory (16 bits here) has nothing to do with the number of address lines. Width decides the number of data lines; length decides the number of address lines. Do not mix them up.

Power-of-two prefixes you must know: $1\text{K} = 2^{10}$, $1\text{M} = 2^{20}$, $1\text{G} = 2^{30}$. So $4\text{K} = 2^{12}$ (MARIE’s memory, 12-bit addresses), $64\text{K} = 2^{16}$, $256\text{K} = 2^{18}$, $2\text{M} = 2^{21}$.

Building Memory from Chips

Real memory is assembled from many smaller RAM chips. Given a target memory of $L \times W$ built from chips of size $l \times w$:

1. Chips per row (to get the width): $W / w$ chips placed side by side, all sharing the same address, each supplying $w$ of the $W$ data bits.
2. Number of rows (to get the length): $L / l$ rows stacked on top of each other.
3. Total chips: $\dfrac{L}{l} \times \dfrac{W}{w}$.
4. Address bits: total $= \log_2 L$. Of these, $\log_2 l$ bits go to every chip (location within the chip) and the remaining $\log_2(L/l)$ bits feed a decoder that produces the chip-select signal choosing which row responds.

With the chip-select bits taken from the high-order (leftmost) end of the address, consecutive addresses fill one row of chips before moving to the next (this is high-order interleaving). Using the low-order bits for chip select instead spreads consecutive addresses across rows (low-order interleaving), which lets different rows work in parallel.

Mini-example

MARIE’s 4K × 16 memory from 1K × 8 chips: rows $= 4\text{K}/1\text{K} = 4$, chips per row $= 16/8 = 2$, so 8 chips. Address bits $= \log_2 4096 = 12$: 2 high-order bits drive a 2-to-4 decoder (chip select), and 10 bits ($\log_2 1024$) go to every chip.

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Worked Examples

Exercise 1

Clock frequency and cycle time.

(a) Find the cycle time of an 800 MHz clock and of a 2.5 GHz clock.

(b) On the 800 MHz machine an instruction needs 6 clock cycles. How long does one instruction take?

(c) A clock has a cycle time of 0.5 ns. What is its frequency?

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Solution

Use $t = 1/f$ and $f = 1/t$.

(a)

$$t_{800\,\text{MHz}} = \frac{1}{800 \times 10^6} = 1.25 \times 10^{-9}\ \text{s} = 1.25\ \text{ns}$$$$t_{2.5\,\text{GHz}} = \frac{1}{2.5 \times 10^9} = 0.4 \times 10^{-9}\ \text{s} = 0.4\ \text{ns}$$

(b) $6 \text{ cycles} \times 1.25\ \text{ns} = 7.5\ \text{ns}$ per instruction.

(c)

$$f = \frac{1}{0.5 \times 10^{-9}\ \text{s}} = 2 \times 10^9\ \text{Hz} = 2\ \text{GHz}$$

Check with the shortcut $t = 1000/f_{\text{MHz}}$: $1000/800 = 1.25$ ✓, $1000/2500 = 0.4$ ✓, $1000/2000 = 0.5$ ✓.

Exercise 2

Address lines. How many address lines are needed for each memory?

(a) 4M × 16, word-addressable. (b) 4M × 16, byte-addressable. (c) MARIE’s memory: 4K words of 16 bits, word-addressable. (d) 64K × 8, byte-addressable.

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Solution

Count the addressable units, write the count as a power of 2, and take the exponent.

(a) Units = words $= 4\text{M} = 2^2 \cdot 2^{20} = 2^{22}$ → 22 lines (addresses $0$ to $2^{22}-1$).

(b) Each 16-bit word is 2 bytes, so units = bytes $= 2^{22} \cdot 2^1 = 2^{23}$ → 23 lines.

(c) Units = words $= 4\text{K} = 2^2 \cdot 2^{10} = 2^{12}$ → 12 lines. This is exactly why MARIE’s MAR and PC are 12 bits wide.

(d) Each location is already one byte, so units $= 64\text{K} = 2^6 \cdot 2^{10} = 2^{16}$ → 16 lines.

Check (a): $2^{22} = 4\,194\,304 = 4 \times 1\,048\,576$ ✓.

Exercise 3

Building MARIE’s memory from chips. MARIE’s 4K × 16 memory is built from 1K × 8 RAM chips.

(a) How many chips are needed, and how are they arranged? (b) How many address bits are needed in total, how many go to every chip, and how many are used for chip select? (c) Using high-order bits for chip select, which row of chips holds address $\text{9AB}_{16}$, and which location inside those chips?

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Solution

(a) Width: $16 / 8 = 2$ chips side by side per row (one supplies bits 15–8, the other bits 7–0). Length: $4\text{K} / 1\text{K} = 4$ rows. Total: $4 \times 2 =$ 8 chips.

(b) Total address bits $= \log_2 4096 = 12$. Within a chip: $\log_2 1024 = 10$ bits (A9–A0), wired to all 8 chips. Chip select: $12 - 10 = 2$ bits (A11 A10) into a 2-to-4 decoder, one output per row.

(c) $\text{9AB}_{16} = 1001\ 1010\ 1011_2$.

• High 2 bits A11 A10 $= 10_2 = 2$ → row 2 (the rows hold 000–3FF, 400–7FF, 800–BFF, C00–FFF; $\text{9AB}$ is indeed in 800–BFF ✓).
• Low 10 bits $= 01\ 1010\ 1011_2 = \text{1AB}_{16} = 427$ → location $\text{1AB}_{16}$ inside both chips of row 2.

Check: $2 \times 1024 + 427 = 2475 = \text{9AB}_{16}$ ✓.

Exercise 4

A 2M × 32 word-addressable memory is built from 256K × 8 RAM chips.

(a) How many chips are needed? (b) How many address bits does the memory need? (c) How many of these bits address a location inside a chip, and how many select the row of chips? What size decoder is required?

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Solution

(a) Chips per row $= 32 / 8 = 4$. Rows $= 2\text{M} / 256\text{K} = 2^{21} / 2^{18} = 2^3 = 8$. Total $= 8 \times 4 =$ 32 chips.

(b) $2\text{M} = 2^{21}$ words → 21 address bits.

(c) Within a chip: $256\text{K} = 2^{18}$ → 18 bits. Chip select: $21 - 18 =$ 3 bits, which drive a 3-to-8 decoder (8 outputs, one per row).

Check: $8 \text{ rows} \times 256\text{K} = 2\text{M}$ ✓ and $4 \text{ chips} \times 8 \text{ bits} = 32$ bits ✓.

Exercise 5

(a) MARIE has seven registers: AC (16 bits), MAR (12), MBR (16), PC (12), IR (16), InREG (8), OutREG (8). If each register is built from D flip-flops, how many flip-flops are needed in total?

(b) Why is a register built from D flip-flops rather than SR flip-flops?

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Solution

(a) One D flip-flop per bit:

$$16 + 12 + 16 + 12 + 16 + 8 + 8 = 88 \text{ D flip-flops.}$$

(b) A D flip-flop simply stores whatever is on its input at the clock edge: $Q(t+1) = D$. Loading a register means “copy this word in”, which is exactly D behaviour. An SR flip-flop would need two inputs per bit and has a forbidden input combination ($S = R = 1$), so it is clumsier for plain storage.

Exercise 6

Buses. A system has a CPU, memory and 3 I/O controllers (5 components).

(a) How many separate links would a fully point-to-point design need? How many with a single multipoint bus? (b) On the multipoint bus, what problem arises and how is it solved? (c) The bus has 32 data lines and performs one transfer per cycle at 100 MHz. What is its peak bandwidth in MB/s? (d) Which group of bus lines (data, address, control) carries each of: the value 0023; the address 104; the “memory read” signal?

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Solution

(a) Point-to-point: one link for every pair $= \dfrac{5 \cdot 4}{2} =$ 10 links. Multipoint: 1 shared bus.

(b) Because it is a shared resource, two devices could try to drive the wires at the same time. Access is controlled by protocols built into the hardware (bus arbitration on the control lines): a device must be granted the bus before it transmits.

(c) 32 lines = 4 bytes per transfer; $4\ \text{bytes} \times 100 \times 10^6\ \text{transfers/s} = 400 \times 10^6$ bytes/s $=$ 400 MB/s.

(d) 0023 (a value) → data lines; 104 (a location) → address lines; “memory read” (what to do) → control lines.