7.1 Control Signals, Timing & the Control Unit

Theory: Control Signals, Timing & the Control Unit

In 6.3 we wrote each instruction as a sequence of RTL microoperations such as MAR ← X. But hardware does not read RTL. Each microoperation happens because the control unit raises a particular set of control signals (wires set to 1) during a particular clock cycle. This lesson shows how to turn RTL into control signals, how to draw the timing diagram, and the two ways of building a control unit: hardwired and microprogrammed.

MARIE’s Control Signals

Careful inspection of MARIE’s RTL shows the ALU only ever needs three operations (add, subtract, clear) plus a fourth “do nothing” state. Together with the bus and the clock, the complete set of control signals is:

The register numbers are the bus device numbers from 6.2:

A signal appears in a signal list only when it is 1. For example, “write the MBR” means $P_5 P_4 P_3 = 011$, so we list $P_4\ P_3$ (and not $P_5$).

Each register has a read (data out) enable and a write (data in) enable. The P lines go through decoders: the 3-bit read code turns on exactly one register’s output onto the bus, the 3-bit write code turns on exactly one register’s load input. In the same cycle one register sends and one register receives.

Deriving the Signal Sequence for an Instruction

1. Write the instruction’s RTL (skip fetch/decode, which use $T_0$–$T_2$; execution starts at $T_3$).
2. Give each microoperation its own clock cycle: $T_3, T_4, T_5, \dots$
3. For each step Dest ← Source:
   • put the source register’s number on $P_2 P_1 P_0$ (list the bits that are 1);
   • put the destination register’s number on $P_5 P_4 P_3$;
   • if the source is memory (M[MAR]), add $M_R$ (memory is device 000, so no P bits);
   • if the destination is memory, add $M_W$;
   • if the step is an ALU operation into the AC, add the $A_1 A_0$ code and $L_{ALT}$ (plus $P_5$ to enable writing the AC).
4. Add the timing signal $T_n$, and add $C_r$ to the last step.

Mini-example (as in the lecture): Add X

P3 P2 P1 P0 T3     : MAR <- X
P4 P3 T4 MR        : MBR <- M[MAR]
Cr A0 P5 T5 LALT   : AC  <- AC + MBR   [reset counter]

These signals are ANDed together by combinational logic to produce the machine’s behaviour.

Timing Diagrams

A timing diagram draws each control signal as a waveform over the clock cycles. A signal is high in exactly those cycles whose signal list contains it. The Add instruction (cycles $C_3$–$C_5$):

Build the diagram row by row from the signal lists: for $P_3$ ask “is $P_3$ in the $T_3$ list? in the $T_4$ list? in the $T_5$ list?” and draw high/low accordingly. $P_3$ is high in both $C_3$ and $C_4$ because both MAR and MBR are written ($001$ and $011$ both have bit 0 set).

Implementing the Control Unit

The control unit keeps things synchronized, making sure the right bits flow to the right components at the right time. There are two general implementations.

Hardwired control

The control logic is built directly from digital logic:

1. The opcode bits IR[15–12] feed an instruction decoder (4 inputs → one AND gate per instruction). The Add gate, for opcode 0011, is

2. A ring counter clocked by the system clock produces the timing signals: exactly one of $T_0, T_1, T_2, \dots$ is high in each cycle, moving one place per clock tick. $C_r$ resets it to $T_0$.
3. Every control signal is an OR of ANDs of (instruction line) · (timing line). For Add alone:
   • $\text{Add}\cdot T_3$ drives $P_0, P_1, P_2, P_3$;
   • $\text{Add}\cdot T_4$ drives $P_3, P_4, M_R$;
   • $\text{Add}\cdot T_5$ drives $P_5, A_0, C_r, L_{ALT}$.

So, for instance, $P_3 = \text{Add}\cdot T_3 + \text{Add}\cdot T_4 + (\text{terms from other instructions})$.

Microprogrammed control

Instead of wiring the logic, store it as a program: each machine instruction is carried out by a short sequence of microinstructions (its microcode), kept in a fast ROM called the control store (this firmware is the microprogram).

• A microinstruction address generator (using the IR and status flags) selects a microinstruction.
• The microinstruction is fetched from the control store into a microinstruction buffer, decoded, and its control signals are sent to the datapath.
• One microinstruction is retrieved during each clock cycle.

A microprogrammed control unit works like a computer in miniature: microinstructions are fetched, decoded and executed just like ordinary instructions.

MARIE’s 18-bit microinstruction format

 17       13 12        8    7    6            0
+-----------+-----------+------+---------------+
| MicroOp1  | MicroOp2  | Jump |     Dest      |
|  5 bits   |  5 bits   | 1 bit|    7 bits     |
+-----------+-----------+------+---------------+

• MicroOp1, MicroOp2: two microoperation codes (5 bits each) carried out in the same cycle (NOP = 00000 if unused).
• Jump: if 1, the Dest field must be a valid microprogram address for the control to branch to.
• Dest: 7-bit address. MARIE’s microprogram has fewer than 128 lines, so $2^7 = 128$ addresses suffice.

Microoperation codes (Table 4.9)

The start of MARIE’s microprogram (Fig. 4.23)

• Lines 0–3 are the fetch–decode cycle (one microoperation per line, Jump = 0 so control just falls through to the next line).
• Lines 4 onward form a jump table: each line compares the opcode IR[15–12] with bits 4–1 of MicroOp2 (00000 → 0000 JnS, 00010 → 0001 Load, 00100 → 0010 Store, 00110 → 0011 Add, 01000 → 0100 Subt). On a match it jumps to the routine for that instruction: JnS at 0100000 (32), Load at 0100111 (39), Store at 0101010 (42), Add at 0101100 (44), Subt at 0101111 (47).
• Each instruction’s routine ends with Jump = 1, Dest = 0000000, which returns to line 0 to fetch the next instruction.

Mini-example

The routines for Store and Add (continuing Fig. 4.23):

Store uses both MicroOp fields in its first line, doing two microoperations in one cycle.

Hardwired vs Microprogrammed

How Many Instructions? RISC vs CISC

The number of instructions an ISA supports is a fundamental design trade-off.

Mini-example

With 16-bit instructions: 15 instructions need a 4-bit opcode, leaving 12 address bits ($2^{12} = 4\text{K}$ words). 509 instructions need a 9-bit opcode, leaving only 7 address bits ($2^7 = 128$ words): the instructions would have to grow or rely on registers.

Worked Examples

P3 P2 P1 P0 T3   : MAR <- X
P4 P3 P2 T4      : MBR <- AC
P1 P0 T5 MW Cr   : M[MAR] <- MBR   [reset counter]